The present invention relates to a semiconductor memory device; and, more particularly, to a circuit performing an ODT (on-die termination) operation in a semiconductor memory device.
In a system having different semiconductor devices which perform various functions, a semiconductor memory device is used as an apparatus for storing data. The semiconductor memory device outputs data, which are correspondent to address inputted from data processing unit to request for the data, for example, a central processing unit and stores in a unit cell the data which are delivered from the data processing unit based on the corresponding address.
As the operation speed of the system becomes higher, the data input/output speed which is required in the data processing unit of the system requests is enhanced more and more. However, in the development of the semiconductor IC until recent date, the data input/output speed between the data processing unit and the semiconductor memory device does not follow the operation speed required within the data processing unit.
Different semiconductor memory devices have been developed in order to increase the data input/output speed to a degree which the data processing unit requires. Synchronous memory devices, which output data in synchronization with the system clock signals provided from the data processing unit, are introduced recently. The synchronous memory device receiving the system clock signal outputs the data to the data processing unit based on a time period of the system clock signal and also receives the data from the data processing unit based on a time period of the system clock signal. However, since this synchronous memory device is not still sufficient for the operation speed of the data processing unit, DDR synchronous memory devices have been developed these days. In DDR synchronous memory devices, the data input and output are carried out based on the transition of the system clock signal. That is, the data input and output of the DDR synchronous memory devices are executed in response to the rising edge and the falling edge of the system clock signal.
On the other hand, various methods for inputting/outputting the data in a high speed between the data processing unit and the semiconductor memory device have been developed. In particular, the data input/output speed between the data processing unit and the semiconductor memory device is increased by controlling impedance on input/output pads through which the data of the semiconductor memory device are inputted and outputted. In the most common technique of the impedance control in the semiconductor memory device, a termination resistance is connected to a node into which data are inputted and the node is to be impedance-controlled to increase the high rate data transmission in the semiconductor memory device.
The termination resistance had been disposed on the PCB (printed circuit board) on which the semiconductor memory device is mounted; however, these semiconductor memory device has the termination resistance within its own inner circuit. The termination resistance included in the semiconductor memory device is called “On-die Termination.” Also, a control signal, which controls the termination resistance included in the semiconductor memory device, is provided from an external circuit. ODT technique is to dispose the termination resistance in the semiconductor memory device. That is, the ODT technique is to make the data transmission fast by connecting the termination resistance to a data receiving side in transferring the data between the data processing unit and the semiconductor memory device. Particularly, this ODT technique is useful in a graphic memory required to transfer the data in a high speed.
FIG. 1 is a table showing an ODT operation time based on the JEDEC specification, particularly the ODT operation time described in the DDR3 specification. FIG. 2 is a waveform illustrating an ODT operation shown in FIG. 1. Since the semiconductor memory device manufactured in compliance with the DDR2 specification typically has the clock frequency of 533 MHz or 667 MHz, there is no a burden on the clock timing parameter relatively. However, since the semiconductor memory device based on the high-speed DDR3 specification has the clock frequency of 800 MHz, 1066 MHz, 1333 MHz or 1600 MHz, it is more difficult to develop a semiconductor memory device in which the ODT timing parameter complies with the specification. As shown in FIG. 1, a point of time of an activation and inactivation of the ODT operation is determined by the following equation: WL−2.0=CWL+AL−2.0.
An issue on the ODT timing becomes important more and more. The ODT operation is classified into a synchronous mode and an asynchronous mode. In actual operation, this is recognized by a power down of a memory device or by an activation of a delay locked loop. The asynchronous mode is easy to satisfy the DDR3 specification because a time which it takes to turn on and off the ODT circuit is one of 1 to 9 ns. However, since the semiconductor memory device in the synchronous mode should operate in synchronization with the clock signals, it is not easy to implement the synchronous semiconductor memory device. Thereafter, the synchronous semiconductor memory devices will be illustrated.
FIG. 2 is a timing chart of a synchronous ODT operation. Referring to FIG. 1, when an ODT operation signal ODT from an externals circuit is activated into a semiconductor memory device in a high level, a termination resistance is connected to an ODT node, of which the impedance is to be controlled, after a lapse of clock time by CWL+AL−2.0. The ODT node is a node to which data input/output pads are connected in order to receive the data from an external circuit. Also, when the ODT operation signal ODT is inactivated to a low level, the termination resistance is disconnected to the ODT node after a lapse of clock time by CWL+AL−2.0. Here, CWL is a column address strobe (CAS) latency. That is, CWL means a time which it takes to start the data storage into the semiconductor memory device after a write command has been executed. AL is an active latency and this means a time which it takes to execute the actual write operation after a point of time the write command is inputted. FIG. 2 is a timing chart in the case where AL is 3 and CWL is 5. That is, the termination resistance is connected to the ODT node after six clock signals from the activation of the ODT operation signal ODT. When the ODT operation signal ODT is inactivated, the termination resistance is disconnected to the ODT node after six clock signals. Eventually, the termination resistance is connected to the ODT node faster than the data input by two clock signals. An inner ODT operation signal IntODT is created when the ODT operation signal ODT is inputted into the semiconductor memory device.
The ODT operation timing, i.e., the time the termination resistance is connected to the ODT node, is in compliance with the range prescribed in the specification and tAONmin, tAONmax, tAOFmin and tAOFmax are correspondent to the parameters of the ODT timing. The tAONmin parameter is a value taken by measuring a time in a direction of (−) centering a reference clock signal which is set up by the ODT latency ODTLon and the tAONmax parameter is a value taken by measuring a time in a direction of (+) centering a reference clock signal which is set up by the ODT latency ODTLon. The tAOFmin parameter is a smallest one of values taken by measuring a time in a direction of (+) centering a reference clock signal which is set up by the ODT turn-off latency ODTLoff and the tAOFmax parameter is a largest one of values taken by measuring a time in a direction of (+) centering a reference clock signal which is set up by the ODT turn-off latency ODTLoff.
Meanwhile, the dynamic ODT operation is further introduced in the DDR3 specification. When a write command is inputted after the termination resistance is connected to the ODT node by the ODT operation, the termination resistance is disconnected from the ODT node at the time of the write operation and an additional termination resistance is connected to the ODT node by the dynamic ODT operation. Accordingly, in order to make the dynamic ODT operation satisfy the specification, a timing required to change the termination resistance connected to the ODT mode into the write termination resistance should be appropriately controlled. The reason why the dynamic ODT operation is further added is that different ODT operations can be executed on a module on which the semiconductor memory devices manufactured according to the specification are disposed. For example, the semiconductor memory devices, which are disposed on the module, can be classified into ranks and the termination operation is carried out in the semiconductor memory device within the adjacent rank when the data are accessed in a selected rank. For the dynamic ODT operation, the module is classified into four ranks.
In addition, there are dynamic ODT timing parameters such as tADCmin and tADCmax. In the case where the dynamic ODT function is supported, the tADCmin parameter is the smallest one of values taken by measuring a time in a direction of (+) centering a reference clock signal which is set up by the dynamic ODT turn-on latency ODTLcnw and the tADCmax parameter is the largest one of values taken by measuring a time in a direction of (+), centering a reference clock signal which is set up by the dynamic ODT turn-on latency ODTLcnw.
FIG. 3 is a table showing an ODT AC parameters based on the JEDEC specification. The parameter tAON is in a range of ±225 ps to ±400 ps according to the operation speed. The parameters of tAOF and tADC are in a range of 0.3 tCK to 0.7 tCK. That is, in the case of tAON, tAOF and tADC parameters, the shorter the clock time tCK is, the more it is difficult to satisfy the specification.
The fluctuation of the ODT operation characteristics may be serious according to the processes of the semiconductor memory devices and it may be required to adjust the ODT timing whenever the semiconductor memory devices are manufactured.
Accordingly, a method for effectively adjusting the ODT timing is needed. Particularly, in the case of the high-speed semiconductor memory device, different testing methods capable of adjusting the ODT timing is also needed to cope with the fluctuation of the ODT operation characteristics.